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<span id="openzim-page-title" class="mw-page-title-main"><span class="mw-page-title-main">Programmable logic device</span></span>

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<p>A <b>programmable logic device</b> (<b>PLD</b>) is an <a href="Electronics" title="Electronics">electronic</a> component used to build <a href="Reconfigurable_computing" title="Reconfigurable computing">reconfigurable</a> <a href="Digital_circuits" class="mw-redirect" title="Digital circuits">digital circuits</a>. Unlike digital logic constructed using discrete <a href="Logic_gate" title="Logic gate">logic gates</a> with fixed functions, the function of a PLD is undefined at the time of manufacture. Before the PLD can be used in a circuit it must be programmed to implement the desired function.<sup id="cite_ref-HorowitzHillArts2015_1-0" class="reference"><a href="#cite_note-HorowitzHillArts2015-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup> Compared to fixed logic devices, programmable logic devices simplify the design of complex logic and may offer superior performance.<sup id="cite_ref-2" class="reference"><a href="#cite_note-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup> Unlike for <a href="Microprocessors" class="mw-redirect" title="Microprocessors">microprocessors</a>, programming a PLD changes the connections made between the gates in the device.

</p><p>PLDs can broadly be categorised into, in increasing order of complexity, <a href="Simple_programmable_logic_device" title="Simple programmable logic device">simple programmable logic devices (SPLDs)</a>, comprising <a href="Programmable_array_logic" class="mw-redirect" title="Programmable array logic">programmable array logic</a>, <a href="Programmable_logic_array" title="Programmable logic array">programmable logic array</a> and <a href="Generic_array_logic" class="mw-redirect" title="Generic array logic">generic array logic</a>; <a href="Complex_programmable_logic_device" title="Complex programmable logic device">complex programmable logic devices (CPLDs)</a>; and <a href="Field-Programmable_Gate_Array" class="mw-redirect" title="Field-Programmable Gate Array">field-programmable gate arrays (FPGAs)</a>.

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<div class="mw-heading mw-heading2"><h2 id="History">History</h2></div>

<p>In 1969, <a href="Motorola" title="Motorola">Motorola</a> offered the XC157, a mask-programmed gate array with 12 gates and 30 uncommitted input/output pins.<sup id="cite_ref-Motorola_XC173_3-0" class="reference"><a href="#cite_note-Motorola_XC173-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup>

</p><p>In 1970, <a href="Texas_Instruments" title="Texas Instruments">Texas Instruments</a> developed a mask-programmable IC based on the <a href="IBM" title="IBM">IBM</a> read-only associative memory or ROAM. This device, the TMS2000, was programmed by altering the metal layer during the production of the IC. The TMS2000 had up to 17 inputs and 18 outputs with 8 <a href="JK_flip-flop" class="mw-redirect" title="JK flip-flop">JK flip-flops</a> for memory. TI coined the term <i><a href="Programmable_logic_array" title="Programmable logic array">programmable logic array</a></i> (PLA) for this device.<sup id="cite_ref-TI_PLA_1970_4-0" class="reference"><a href="#cite_note-TI_PLA_1970-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup>

</p><p>In 1971, <a href="General_Electric" title="General Electric">General Electric</a> Company (GE) was developing a programmable logic device based on the new <a href="Programmable_read-only_memory" class="mw-redirect" title="Programmable read-only memory">programmable read-only memory</a> (PROM) technology. This experimental device improved on IBM's ROAM by allowing multilevel logic. Intel had just introduced the floating-gate <a href="UV_EPROM" class="mw-redirect" title="UV EPROM">UV EPROM</a> so the researcher at GE incorporated that technology. The GE device was the first erasable PLD ever developed, predating the <a href="Altera" title="Altera">Altera</a> EPLD by over a decade. GE obtained several early patents on programmable logic devices.<sup id="cite_ref-US_Patents_3,818,452_5-0" class="reference"><a href="#cite_note-US_Patents_3,818,452-5"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-US_Patents_3,816,725_6-0" class="reference"><a href="#cite_note-US_Patents_3,816,725-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-US_Patents_3,849,638_7-0" class="reference"><a href="#cite_note-US_Patents_3,849,638-7"><span class="cite-bracket">[</span>7<span class="cite-bracket">]</span></a></sup>

</p><p>In 1973 <a href="National_Semiconductor" title="National Semiconductor">National Semiconductor</a> introduced a mask-programmable PLA device (DM7575) with 14 inputs and 8 outputs with no memory registers. This was more popular than the TI part but the cost of making the metal mask limited its use. The device is significant because it was the basis for the field programmable logic array produced by <a href="Signetics" title="Signetics">Signetics</a> in 1975, the 82S100. (<a href="Intersil" title="Intersil">Intersil</a> actually beat Signetics to market but poor yield doomed their part.)<sup id="cite_ref-Intersil_IM5200_8-0" class="reference"><a href="#cite_note-Intersil_IM5200-8"><span class="cite-bracket">[</span>8<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-Signetics_82S100_9-0" class="reference"><a href="#cite_note-Signetics_82S100-9"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup>

</p><p>In 1974 GE entered into an agreement with <a href="Monolithic_Memories" title="Monolithic Memories">Monolithic Memories</a> (MMI) to develop a mask-programmable logic device incorporating the GE innovations. The device was named <i>programmable associative logic array</i> or PALA. The MMI 5760 was completed in 1976 and could implement multilevel or sequential circuits of over 100 gates. The device was supported by a GE design environment where Boolean equations would be converted to mask patterns for configuring the device. The part was never brought to market.<sup id="cite_ref-Pellerin_1991_10-0" class="reference"><a href="#cite_note-Pellerin_1991-10"><span class="cite-bracket">[</span>10<span class="cite-bracket">]</span></a></sup>

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</style><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="Programmable_logic_array" title="Programmable logic array">Programmable logic array</a></div>

<p>In 1970, <a href="Texas_Instruments" title="Texas Instruments">Texas Instruments</a> developed a mask-programmable IC based on the <a href="IBM" title="IBM">IBM</a> read-only associative memory or ROAM. This device, the TMS2000, was programmed by altering the metal layer during the production of the IC. The TMS2000 had up to 17 inputs and 18 outputs with 8 <a href="JK_flip-flops" class="mw-redirect" title="JK flip-flops">JK flip-flops</a> for memory. TI coined the term <a href="Programmable_logic_array" title="Programmable logic array">programmable logic array</a> for this device.<sup id="cite_ref-TI_PLA_1970_4-1" class="reference"><a href="#cite_note-TI_PLA_1970-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup>

</p><p>A programmable logic array (PLA) has a programmable AND gate array, which links to a programmable OR gate array, which can then be conditionally complemented to produce an output. A PLA is similar to a ROM concept, however a PLA does not provide full decoding of a variable and does not generate all the <a href="Minterms" class="mw-redirect" title="Minterms">minterms</a> as in a ROM.

</p><p>The programmable logic sequencer (PLS/FPLS) is similar to a PLA, but with integral registered outputs using a number of <a href="Flip-flops" title="Flip-flops">flip-flops</a> to allow creation of some <a href="State_machine" class="mw-redirect" title="State machine">state machines</a>. <a href="Signetics" title="Signetics">Signetics</a> introduced the first FPLS in 1979.<sup id="cite_ref-Alford_1989_11-0" class="reference"><a href="#cite_note-Alford_1989-11"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup>

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<div role="note" class="hatnote navigation-not-searchable">Main article: <a href="Programmable_array_logic" class="mw-redirect" title="Programmable array logic">Programmable array logic</a></div>

<p>PAL devices have arrays of transistor cells arranged in a "fixed-OR, programmable-AND" plane used to implement "sum-of-products" binary logic equations for each of the outputs in terms of the inputs and either synchronous or asynchronous feedback from the outputs.

</p><p>MMI introduced a breakthrough device in 1978, the <a href="Programmable_array_logic" class="mw-redirect" title="Programmable array logic">programmable array logic</a> or PAL. The architecture was simpler than that of Signetics' FPLA because it omitted the programmable OR array. This made the parts faster, smaller and cheaper. They were available in 20-pin 300-mil DIP packages, while the FPLAs came in 28-pin 600-mil packages. The PAL Handbook demystified the design process. The PALASM design software (PAL assembler) converted the engineers' Boolean equations into the fuse pattern required to program the part. The PAL devices were soon <a href="Second_source" title="Second source">second-sourced</a> by National Semiconductor, Texas Instruments and AMD.

</p><p>After MMI succeeded with the 20-pin PAL parts, <a href="AMD" title="AMD">AMD</a> introduced the 24-pin 22V10 PAL with additional features. After buying out MMI (1987), AMD spun off a consolidated operation as <a href="Vantis" title="Vantis">Vantis</a>, and that business was acquired by <a href="Lattice_Semiconductor" title="Lattice Semiconductor">Lattice Semiconductor</a> in 1999.

</p>

<div role="note" class="hatnote navigation-not-searchable">Main article: <a href="Generic_array_logic" class="mw-redirect" title="Generic array logic">Generic array logic</a></div>

<p>An improvement on the PAL was the generic array logic device, or GAL, invented by <a href="Lattice_Semiconductor" title="Lattice Semiconductor">Lattice Semiconductor</a> in 1985. This device has the same logical properties as the PAL but can be erased and reprogrammed. The GAL is very useful in the prototyping stage of a design when any <a href="Computer_bug" class="mw-redirect" title="Computer bug">bugs</a> in the logic can be corrected by reprogramming. GALs are programmed and reprogrammed using a PAL programmer, or, in the case of chips that support it, by using the <a href="In-circuit_programming" class="mw-redirect" title="In-circuit programming">in-circuit programming</a> technique.

</p><p>Lattice GALs combine <a href="CMOS" title="CMOS">CMOS</a> and electrically erasable (E<sup>2</sup>) floating gate technology for a high-speed, low-power logic device. A similar device called a PEEL (programmable electrically erasable logic) was introduced by the International CMOS Technology (ICT) corporation.

</p><p>Sometimes GAL chips are referred as simple programmable logic device (SPLD), analogous to complex programmable logic device (CPLD) below.

</p>

<div class="mw-heading mw-heading2"><h2 id="CPLDs">CPLDs</h2></div>

<div role="note" class="hatnote navigation-not-searchable">Main article: <a href="Complex_programmable_logic_device" title="Complex programmable logic device">Complex programmable logic device</a></div>

<p>PALs and GALs are available only in small sizes, equivalent to a few hundred logic gates. For bigger logic circuits, complex PLDs or <a href="CPLD" class="mw-redirect" title="CPLD">CPLDs</a> can be used. These contain the equivalent of several PALs linked by programmable interconnections, all in one <a href="Integrated_circuit" title="Integrated circuit">integrated circuit</a>. CPLDs can replace thousands, or even hundreds of thousands, of logic gates.

</p><p>Some CPLDs are programmed using a PAL programmer, but this method becomes inconvenient for devices with hundreds of pins. A second method of programming is to solder the device to its printed circuit board, then feed it with a serial data stream from a personal computer. The CPLD contains a circuit that decodes the data stream and configures the CPLD to perform its specified logic function. Some manufacturers, such as <a href="Altera" title="Altera">Altera</a> and <a href="Atmel" title="Atmel">Atmel (now Microchip)</a>, use <a href="JTAG" title="JTAG">JTAG</a> to program CPLDs in-circuit from <a href="Standard_Test_and_Programming_Language" title="Standard Test and Programming Language">.JAM</a> files.

</p>

<div class="mw-heading mw-heading2"><h2 id="FPGAs">FPGAs</h2></div>

<div role="note" class="hatnote navigation-not-searchable">Main article: <a href="Field-programmable_gate_array" title="Field-programmable gate array">Field-programmable gate array</a></div>

<p>While PALs were being developed into GALs and CPLDs (all discussed above), a separate stream of development was happening. This type of device is based on <a href="Gate_array" title="Gate array">gate array</a> technology and is called the <a href="Field-programmable_gate_array" title="Field-programmable gate array">field-programmable gate array</a> (FPGA). Early examples of FPGAs are the 82S100 array, and 82S105 sequencer, by Signetics, introduced in the late 1970s. The 82S100 was an array of AND terms. The 82S105 also had flip-flop functions.

</p><p>(Remark: 82S100 and similar ICs from Signetics have PLA structure, AND-plane + OR-plane.)

</p><p>FPGAs use a grid of <a href="Logic_gate" title="Logic gate">logic gates</a>, and once stored, the data doesn't change, similar to that of an ordinary gate array. The term <i>field-programmable</i> means the device is programmed by the customer, not the manufacturer. FPGAs and gate arrays are similar but gate arrays can only be configured at the factory during fabrication.<sup id="cite_ref-12" class="reference"><a href="#cite_note-12"><span class="cite-bracket">[</span>12<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-13" class="reference"><a href="#cite_note-13"><span class="cite-bracket">[</span>13<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-14" class="reference"><a href="#cite_note-14"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup>

</p><p>FPGAs are usually programmed after being soldered down to the circuit board, in a manner similar to that of larger CPLDs. In most larger FPGAs, the configuration is volatile and must be re-loaded into the device whenever power is applied or different functionality is required. Configuration is typically stored in a configuration <a href="Programmable_read-only_memory" class="mw-redirect" title="Programmable read-only memory">PROM</a>, <a href="EEPROM" title="EEPROM">EEPROM</a> or flash memory.<sup id="cite_ref-15" class="reference"><a href="#cite_note-15"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup> EEPROM versions may be in-system programmable (typically via <a href="JTAG" title="JTAG">JTAG</a>).

</p><p>The difference between FPGAs and CPLDs is that FPGAs are internally based on <a href="Lookup_table" title="Lookup table">look-up tables</a> (LUTs), whereas CPLDs form the logic functions with sea-of-gates (e.g. <a href="Canonical_normal_form" title="Canonical normal form">sum of products</a>). CPLDs are meant for simpler designs while FPGAs are meant for more complex designs. In general, CPLDs are a good choice for wide <a href="Combinational_logic" title="Combinational logic">combinational logic</a> applications, whereas FPGAs are more suitable for large <a href="State_machine" class="mw-redirect" title="State machine">state machines</a> such as <a href="Microprocessors" class="mw-redirect" title="Microprocessors">microprocessors</a>.

</p>

<div class="mw-heading mw-heading2"><h2 id="EPLDs">EPLDs</h2></div>

<p>Using the same technology as <a href="EPROM" title="EPROM">EPROMs</a>, <b>EPLD</b>s have a quartz window in the package that allows them to be erased on exposure to UV light.<sup id="cite_ref-Ndjountche_16-0" class="reference"><a href="#cite_note-Ndjountche-16"><span class="cite-bracket">[</span>16<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-Maxfield_17-0" class="reference"><a href="#cite_note-Maxfield-17"><span class="cite-bracket">[</span>17<span class="cite-bracket">]</span></a></sup>

</p><p>Using the same technology as <a href="EEPROM" title="EEPROM">EEPROMs</a>, <b>EEPLDs</b> can be erased electrically.<sup id="cite_ref-Ndjountche_16-1" class="reference"><a href="#cite_note-Ndjountche-16"><span class="cite-bracket">[</span>16<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-Maxfield_17-1" class="reference"><a href="#cite_note-Maxfield-17"><span class="cite-bracket">[</span>17<span class="cite-bracket">]</span></a></sup>

</p><p>An <b>erasable programmable logic device</b> (<b>EPLD</b>) is an integrated circuit that comprises an array of PLDs that do not come pre-connected; the connections are programmed electrically by the user. Most GAL and FPGA devices are examples of EPLDs.

</p>

<div class="mw-heading mw-heading2"><h2 id="Other_variants">Other variants</h2></div>

<p>These are microprocessor circuits that contain some <a href="Fixed-function" class="mw-redirect" title="Fixed-function">fixed functions</a> and other functions that can be altered by code running on the processor. Designing self-altering systems requires that engineers learn new methods and that new software tools be developed.

</p><p>PLDs are being sold now that contain a microprocessor with a fixed function (the so-called <i>core</i>) surrounded by programmable logic. These devices let designers concentrate on adding new features to designs without having to worry about making the microprocessor work. Also, the fixed-function microprocessor takes less space on the chip than a part of the programmable gate array implementing the same processor, leaving more space for the programmable gate array to contain the designer's specialized circuits.

</p>

<div class="mw-heading mw-heading2"><h2 id="How_PLDs_retain_their_configuration">How PLDs retain their configuration</h2></div>

<p>A PLD is a combination of a logic device and a <a href="Computer_memory" title="Computer memory">memory</a> device. The memory is used to store the pattern that was given to the chip during programming. Most of the methods for storing data in an integrated circuit have been adapted for use in PLDs. These include:

</p>

<ul><li><a href="Silicon" title="Silicon">Silicon</a> <a href="Antifuse" title="Antifuse">antifuses</a></li>

<li><a href="EPROM" title="EPROM">EPROM</a> or <a href="EEPROM" title="EEPROM">EEPROM</a> <a href="Memory_cell_(computing)" title="Memory cell (computing)">memory cells</a></li>

<li><a href="Flash_memory" title="Flash memory">Flash memory</a></li></ul>

<p>Silicon antifuses are connections that are made by applying a voltage across a modified area of silicon inside the chip. They are called <i>antifuses</i> because they work in the opposite way to normal fuses, which begin life as connections until they are broken by an electric current.

</p><p>SRAM, or static RAM, is a volatile type of memory, meaning that its contents are lost each time the power is switched off. SRAM-based PLDs therefore have to be programmed every time the circuit is switched on. This is usually done automatically by another part of the circuit.

</p><p>An EPROM memory cell is a <a href="MOSFET" title="MOSFET">MOSFET</a> (metal-oxide-semiconductor field-effect transistor, or MOS transistor) that can be switched on by trapping an electric charge permanently on its gate electrode. This is done by a PAL programmer. The charge remains for many years and can only be removed by exposing the chip to strong <a href="Ultraviolet" title="Ultraviolet">ultraviolet</a> light in a device called an EPROM eraser.

</p><p>Flash memory is non-volatile, retaining its contents even when the power is switched off. It is stored on <a href="Floating-gate_MOSFET" title="Floating-gate MOSFET">floating-gate MOSFET</a> memory cells, and can be erased and reprogrammed as required. This makes it useful in PLDs that may be reprogrammed frequently, such as PLDs used in prototypes. Flash memory is a kind of EEPROM that holds information using trapped electric charges similar to EPROM. Consequently, flash memory can hold information for years, but possibly not as many years as EPROM.

</p><p>As of 2005, most CPLDs are electrically programmable and erasable, and non-volatile. This is because they are too small to justify the inconvenience of programming internal SRAM cells every time they start up, and EPROM cells are more expensive due to their ceramic package with a quartz window.

</p>

<div class="mw-heading mw-heading2"><h2 id="PLD_programming_languages">PLD programming languages</h2></div>

<p>Many PAL programming devices accept input in a standard file format, commonly referred to as '<a href="JEDEC" title="JEDEC">JEDEC</a> files'. They are analogous to <a href="Software" title="Software">software</a> <a href="Compiler" title="Compiler">compilers</a>. The languages used as <a href="Source_code" title="Source code">source code</a> for logic compilers are called <a href="Hardware_description_language" title="Hardware description language">hardware description languages</a>, or HDLs.<sup id="cite_ref-HorowitzHillArts2015_1-1" class="reference"><a href="#cite_note-HorowitzHillArts2015-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup>

</p><p><a href="PALASM" title="PALASM">PALASM</a>, <a href="Advanced_Boolean_Expression_Language" title="Advanced Boolean Expression Language">ABEL</a> and <a href="Programmable_Array_Logic#CUPL" title="Programmable Array Logic">CUPL</a> are frequently used for low-complexity devices, while <a href="Verilog" title="Verilog">Verilog</a> and <a href="VHDL" title="VHDL">VHDL</a> are popular higher-level description languages for more complex devices. The more limited ABEL is often used for historical reasons, but for new designs, VHDL is more popular, even for low-complexity designs.

</p><p>For modern PLD programming languages, design flows, and tools, see <a href="FPGA" class="mw-redirect" title="FPGA">FPGA</a> and <a href="Reconfigurable_computing" title="Reconfigurable computing">reconfigurable computing</a>.

</p>

<div class="mw-heading mw-heading2"><h2 id="PLD_programming_devices">PLD programming devices</h2></div>

<p>A <a href="Device_programmer" class="mw-redirect" title="Device programmer">device programmer</a> is used to transfer the Boolean logic pattern into the programmable device. In the early days of programmable logic, every PLD manufacturer also produced a specialized device programmer for its family of logic devices. Later, universal device programmers came onto the market that supported several logic device families from different manufacturers. Today's device programmers usually can program common PLDs (mostly PAL/GAL equivalents) from all existing manufacturers. Common file formats used to store the Boolean logic pattern (fuses) are JEDEC, Altera POF (programmable object file), or Xilinx BITstream.<sup id="cite_ref-18" class="reference"><a href="#cite_note-18"><span class="cite-bracket">[</span>18<span class="cite-bracket">]</span></a></sup>

</p>

<ul><li><a href="Complex_programmable_logic_device" title="Complex programmable logic device">Complex programmable logic device</a> (CPLD)</li>

<li><a href="Field-programmable_gate_array" title="Field-programmable gate array">Field-programmable gate array</a> (FPGA)</li>

<li><a href="Macrocell_array" title="Macrocell array">Macrocell array</a></li>

<li><a href="Programmable_array_logic" class="mw-redirect" title="Programmable array logic">Programmable array logic</a> (PAL)</li></ul>

<div class="mw-heading mw-heading2"><h2 id="References">References</h2></div>

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</style><cite id="CITEREFHorowitzHill2015" class="citation book cs1">Horowitz, Paul; Hill, Winfield (2015). <i>Horowitz P., Hill W. - The Art of Electronics</i>. New York. p. 764. <a href="ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <bdi>978-0-521-80926-9</bdi>.</cite><span class="cs1-maint citation-comment"><code class="cs1-code">{{cite book}}</code>: CS1 maint: location missing publisher (link)</span></span>

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<li id="cite_note-2"><span class="mw-cite-backlink"><b><a href="#cite_ref-2">^</a></b></span> <span class="reference-text"><cite id="CITEREFHoldsworthWoods2003" class="citation book cs1">Holdsworth, B.; Woods, R. C. (2003). <a rel="nofollow" class="external text" href="https://www.sciencedirect.com/book/9780750645829/digital-logic-design"><i>Digital Logic Design</i></a> (4th ed.). Elsevier. <a href="ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <bdi>978-0-7506-4582-9</bdi>.</cite></span>

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<li id="cite_note-Motorola_XC173-3"><span class="mw-cite-backlink"><b><a href="#cite_ref-Motorola_XC173_3-0">^</a></b></span> <span class="reference-text"><cite class="citation book cs1"><i>Motorola Semiconductor Data Book, Fourth Edition</i>. Motorola Inc. 1969. p. IC-73.</cite></span>

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<li id="cite_note-TI_PLA_1970-4"><span class="mw-cite-backlink">^ <a href="#cite_ref-TI_PLA_1970_4-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-TI_PLA_1970_4-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><cite id="CITEREFAndres1970" class="citation book cs1">Andres, Kent (October 1970). <i>A Texas Instruments Application Report: MOS programmable logic arrays</i>. Texas Instruments. Bulletin CA-158.</cite> Report introduces the TMS2000 and TMS2200 series of mask programmable PLAs.</span>

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<li id="cite_note-US_Patents_3,818,452-5"><span class="mw-cite-backlink"><b><a href="#cite_ref-US_Patents_3,818,452_5-0">^</a></b></span> <span class="reference-text">Greer, David L. <i>Electrically Programmable Logic Circuits</i> <a rel="nofollow" class="external text" href="https://patents.google.com/patent/US3818452">US Patent 3,818,452</a>. Assignee: General Electric, Filed: April 28, 1972, Granted: June 18, 1974</span>

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<li id="cite_note-US_Patents_3,816,725-6"><span class="mw-cite-backlink"><b><a href="#cite_ref-US_Patents_3,816,725_6-0">^</a></b></span> <span class="reference-text">Greer, David L. <i>Multiple Level Associative Logic Circuits</i> <a rel="nofollow" class="external text" href="https://patents.google.com/patent/US3816725">US Patent 3,816,725</a>. Assignee: General Electric, Filed: April 28, 1972, Granted: June 11, 1974</span>

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<li id="cite_note-US_Patents_3,849,638-7"><span class="mw-cite-backlink"><b><a href="#cite_ref-US_Patents_3,849,638_7-0">^</a></b></span> <span class="reference-text">Greer, David L. <i>Segmented Associative Logic Circuits</i> <a rel="nofollow" class="external text" href="https://patents.google.com/patent/US3849638">US Patent 3,849,638</a>. Assignee: General Electric, Filed: July 18, 1973, Granted: November 19, 1974</span>

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<li id="cite_note-Intersil_IM5200-8"><span class="mw-cite-backlink"><b><a href="#cite_ref-Intersil_IM5200_8-0">^</a></b></span> <span class="reference-text"><cite class="citation journal cs1">"Semiconductors and IC's : FPLA". <i>EDN</i>. <b>20</b> (13). Boston, MA: Cahners Publishing: 66. July 20, 1975.</cite> Press release on Intersil IM5200 field programmable logic array. Fourteen inputs pins and 48 product terms. Avalanched-induced-migration programming. Unit price was $37.50</span>

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<li id="cite_note-Signetics_82S100-9"><span class="mw-cite-backlink"><b><a href="#cite_ref-Signetics_82S100_9-0">^</a></b></span> <span class="reference-text"><cite class="citation journal cs1">"FPLA's give quick custom logic". <i>EDN</i>. <b>20</b> (13). Boston, MA: Cahners Publishing: 61. July 20, 1975.</cite> Press release on Signetics 82S100 and 82S101 field programmable logic arrays. Fourteen inputs pins, 8 output pins and 48 product terms. NiCr fuse link programming.</span>

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<li id="cite_note-Pellerin_1991-10"><span class="mw-cite-backlink"><b><a href="#cite_ref-Pellerin_1991_10-0">^</a></b></span> <span class="reference-text"><cite id="CITEREFPellerinMichael_Holley1991" class="citation book cs1">Pellerin, David; Michael Holley (1991). <i>Practical Design Using Programmable Logic</i>. Prentice-Hall. p. 15. <a href="ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <bdi>0-13-723834-7</bdi>.</cite></span>

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<li id="cite_note-Alford_1989-11"><span class="mw-cite-backlink"><b><a href="#cite_ref-Alford_1989_11-0">^</a></b></span> <span class="reference-text"><cite id="CITEREFAlford1989" class="citation book cs1">Alford, Roger C. (1989). <a rel="nofollow" class="external text" href="https://archive.org/details/programmablelogi0000alfo/"><i>Programmable Logic Designer's Guide</i></a>. Howard W. Sams. pp. <span class="nowrap">67–</span>69. <a href="ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <bdi>0-672-22575-1</bdi>. <q>The registers can be dynamically or permanently configured as D, J-K, or T flip-flops, because of the flexibility offered by the inclusion of the "M" inverters (M<sub>0</sub>-M<sub>5</sub>). The outputs of the registers are fed back into the AND-array <i>before</i> reaching the tri-state output buffers, allowing for Mealy and Moore state machine development.</q></cite></span>

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<li id="cite_note-12"><span class="mw-cite-backlink"><b><a href="#cite_ref-12">^</a></b></span> <span class="reference-text"><cite id="CITEREFDorf2018" class="citation book cs1">Dorf, Richard C. (3 October 2018). <a rel="nofollow" class="external text" href="https://books.google.com/books?id=mZRsBgAAQBAJ&dq=gate+array+custom&pg=SA4-PA28"><i>Electronics, Power Electronics, Optoelectronics, Microwaves, Electromagnetics, and Radar</i></a>. CRC Press. <a href="ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <bdi>978-1-4200-0315-4</bdi>.</cite></span>

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<li id="cite_note-13"><span class="mw-cite-backlink"><b><a href="#cite_ref-13">^</a></b></span> <span class="reference-text"><cite id="CITEREFVahidGivargis2001" class="citation book cs1">Vahid, Frank; Givargis, Tony D. (17 October 2001). <a rel="nofollow" class="external text" href="https://books.google.com/books?id=ymoCEAAAQBAJ&dq=gate+array+custom&pg=PA276"><i>Embedded System Design: A Unified Hardware / Software Introduction</i></a>. John Wiley & Sons. <a href="ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <bdi>978-0-471-38678-0</bdi>.</cite></span>

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<li id="cite_note-14"><span class="mw-cite-backlink"><b><a href="#cite_ref-14">^</a></b></span> <span class="reference-text"><cite id="CITEREFChen2018" class="citation book cs1">Chen, Wai-Kai (3 October 2018). <a rel="nofollow" class="external text" href="https://books.google.com/books?id=rMsqBgAAQBAJ&dq=gate+array+custom&pg=SA47-PA12"><i>The VLSI Handbook</i></a>. CRC Press. <a href="ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <bdi>978-1-4200-0596-7</bdi>.</cite></span>

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<li id="cite_note-15"><span class="mw-cite-backlink"><b><a href="#cite_ref-15">^</a></b></span> <span class="reference-text"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://cdrdv2-public.intel.com/654742/cfg_cf52010.pdf">"Using Flash Memory to Configure FPGAs"</a> <span class="cs1-format">(PDF)</span>. <a href="Altera" title="Altera">Altera</a><span class="reference-accessdate">. Retrieved <span class="nowrap">2024-08-21</span></span>.</cite></span>

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Tertulien Ndjountche.

<a rel="nofollow" class="external text" href="https://books.google.com/books?id=P7jeDAAAQBAJ">"Digital Electronics 2: Sequential and Arithmetic Logic Circuits"</a>.

2016.

p. 224.</span>

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Clive Maxfield.

<a rel="nofollow" class="external text" href="https://books.google.com/books?id=dnuwr2xOFpUC">"The Design Warrior's Guide to FPGAs"</a>.

2004.

p. 20</span>

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<li id="cite_note-18"><span class="mw-cite-backlink"><b><a href="#cite_ref-18">^</a></b></span> <span class="reference-text"><a rel="nofollow" class="external text" href="http://www.pldtool.com/pld-file-formats">PLD File Formats</a></span>

</li>

</ol></div></div>

<div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2></div>

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<div class="side-box-text plainlist">Wikibooks has a book on the topic of: <i><b><a href="https://en.wikibooks.org/wiki/Programmable_Logic" class="extiw external" title="wikibooks:Programmable Logic">Programmable Logic</a></b></i></div></div>

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<div class="side-box-text plainlist">Wikimedia Commons has media related to <span style="font-weight: bold; font-style: italic;"><a href="https://commons.wikimedia.org/wiki/Category:Programmable_logic_devices" class="extiw external" title="commons:Category:Programmable logic devices">Programmable logic devices</a></span>.</div></div>

</div>

<ul><li><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20120318182807/http://www.corelis.com/blog/index.php/blog/2010/12/01/pld-tools-creating-svf-jam-stapl-and-other-formats">"PLD Tools Creating SVF, JAM, STAPL and other formats"</a>. <i>JTAG / boundary-scan</i>. Corelis. Dec 1, 2010. Archived from <a rel="nofollow" class="external text" href="http://www.corelis.com/blog/index.php/blog/2010/12/01/pld-tools-creating-svf-jam-stapl-and-other-formats">the original</a> on March 18, 2012<span class="reference-accessdate">. Retrieved <span class="nowrap">July 18,</span> 2011</span>.</cite></li>

<li><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.latticesemi.com/Products/FPGAandCPLD.aspx">"FPGAs and CPLDs"</a>. Lattice Semiconductor.</cite></li></ul>

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</style><div id="Programmable_logic116" style="font-size:114%;margin:0 4em"></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%">Concepts</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Logic_block" title="Logic block">Logic block</a></li></ul></li>

<li><a href="Reconfigurable_computing" title="Reconfigurable computing">Reconfigurable computing</a>

<ul><li><a href="Xputer" title="Xputer">Xputer</a></li></ul></li>

<li><a href="Soft_microprocessor" title="Soft microprocessor">Soft microprocessor</a></li>

<li><a href="Circuit_underutilization" title="Circuit underutilization">Circuit underutilization</a></li>

<li><a href="High-level_synthesis" title="High-level synthesis">High-level synthesis</a></li>

<li><a href="Hardware_acceleration" title="Hardware acceleration">Hardware acceleration</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Hardware_description_language" title="Hardware description language">Languages</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Verilog" title="Verilog">Verilog</a>

<li><a href="VHDL-VITAL" class="mw-redirect" title="VHDL-VITAL">VITAL</a></li></ul></li>

<li><a href="SystemVerilog" title="SystemVerilog">SystemVerilog</a>

<li><a href="SystemC" title="SystemC">SystemC</a></li>

<li><a href="Handel-C" title="Handel-C">Handel-C</a></li>

<li><a href="PALASM" title="PALASM">PALASM</a></li>

<li><a href="MyHDL" title="MyHDL">MyHDL</a></li>

<li><a href="Chisel_(programming_language)" title="Chisel (programming language)">Chisel</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Companies</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Accellera" title="Accellera">Accellera</a></li>

<li><a href="Achronix" title="Achronix">Achronix</a></li>

<li><a href="Aldec" title="Aldec">Aldec</a></li>

<li><a href="Cadence_Design_Systems" title="Cadence Design Systems">Cadence</a></li>

<li><a href="Infineon_Technologies" title="Infineon Technologies">Infineon</a></li>

<li><a href="Intel" title="Intel">Intel</a></li>

<li><a href="Lattice_Semiconductor" title="Lattice Semiconductor">Lattice</a></li>

<li><a href="Microchip_Technology" title="Microchip Technology">Microchip Technology</a></li>

<li><a href="Siemens" title="Siemens">Siemens</a></li>

<li><a href="Synopsys" title="Synopsys">Synopsys</a></li>

<li><a href="Texas_Instruments" title="Texas Instruments">Texas Instruments</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Products</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Hardware</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<li><a href="Stratix" title="Stratix">Stratix</a></li>

<li><a href="Virtex_(FPGA)" title="Virtex (FPGA)">Virtex</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Software</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Intel_Quartus_Prime" class="mw-redirect" title="Intel Quartus Prime">Intel Quartus Prime</a></li>

<li><a href="Xilinx_ISE" title="Xilinx ISE">Xilinx ISE</a></li>

<li><a href="Vivado" title="Vivado">Vivado</a></li>

<li><a href="ModelSim" title="ModelSim">ModelSim</a></li>

<li><a href="List_of_HDL_simulators" title="List of HDL simulators">Simulators</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Intellectual_property" title="Intellectual property">Intellectual<br>property</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Proprietary_hardware" title="Proprietary hardware">Proprietary</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<li><a href="ARM_Cortex-M" title="ARM Cortex-M">ARM Cortex-M</a></li>

<li><a href="LatticeMico8" title="LatticeMico8">LatticeMico8</a></li>

<li><a href="MicroBlaze" title="MicroBlaze">MicroBlaze</a></li>

<li><a href="PicoBlaze" title="PicoBlaze">PicoBlaze</a></li>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Open-source_hardware" title="Open-source hardware">Open-source</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<li><a href="LatticeMico32" title="LatticeMico32">LatticeMico32</a></li>

<li><a href="OpenCores" title="OpenCores">OpenCores</a></li>

<li><a href="OpenRISC" title="OpenRISC">OpenRISC</a>

<li><a href="Power_ISA" title="Power ISA">Power ISA</a>

<ul><li><a href="Libre-SOC" title="Libre-SOC">Libre-SOC</a></li>

<li><a href="OpenPOWER_Microwatt" title="OpenPOWER Microwatt">Microwatt</a></li></ul></li>

</div></td></tr></tbody></table><div></div></td></tr></tbody></table><div></div></td></tr></tbody></table></div>

<div class="navbox-styles"></div><div role="navigation" class="navbox" aria-labelledby="Digital_electronics118" style="padding:3px"><table class="nowraplinks mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><div id="Digital_electronics118" style="font-size:114%;margin:0 4em"><a href="Digital_electronics" title="Digital electronics">Digital electronics</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;"><a href="Electronic_component" title="Electronic component">Components</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Transistor" title="Transistor">Transistor</a></li>

<li><a href="Resistor" title="Resistor">Resistor</a></li>

<li><a href="Inductor" title="Inductor">Inductor</a></li>

<li><a href="Capacitor" title="Capacitor">Capacitor</a></li>

<li><a href="Printed_electronics" title="Printed electronics">Printed electronics</a></li>

<li><a href="Printed_circuit_board" title="Printed circuit board">Printed circuit board</a></li>

<li><a href="Electronic_circuit" title="Electronic circuit">Electronic circuit</a></li>

<li><a href="Memory_cell_(computing)" title="Memory cell (computing)">Memory cell</a></li>

<li><a href="Combinational_logic" title="Combinational logic">Combinational logic</a></li>

<li><a href="Sequential_logic" title="Sequential logic">Sequential logic</a></li>

<li><a href="Logic_gate" title="Logic gate">Logic gate</a></li>

<li><a href="Boolean_circuit" title="Boolean circuit">Boolean circuit</a></li>

<li><a href="Integrated_circuit" title="Integrated circuit">Integrated circuit</a> (IC)</li>

<li><a href="Hybrid_integrated_circuit" title="Hybrid integrated circuit">Hybrid integrated circuit</a> (HIC)</li>

<li><a href="Mixed-signal_integrated_circuit" title="Mixed-signal integrated circuit">Mixed-signal integrated circuit</a></li>

<li><a href="Three-dimensional_integrated_circuit" title="Three-dimensional integrated circuit">Three-dimensional integrated circuit</a> (3D IC)</li>

<li><a href="Emitter-coupled_logic" title="Emitter-coupled logic">Emitter-coupled logic</a> (ECL)</li>

<li><a href="Erasable_programmable_logic_device" class="mw-redirect" title="Erasable programmable logic device">Erasable programmable logic device</a> (EPLD)</li>

<li><a href="Macrocell_array" title="Macrocell array">Macrocell array</a></li>

<li><a href="Programmable_logic_array" title="Programmable logic array">Programmable logic array</a> (PLA)</li>

<li><a href="Programmable_Array_Logic" title="Programmable Array Logic">Programmable Array Logic</a> (PAL)</li>

<li><a href="Generic_Array_Logic" title="Generic Array Logic">Generic Array Logic</a> (GAL)</li>

<li><a href="Complex_programmable_logic_device" title="Complex programmable logic device">Complex programmable logic device</a> (CPLD)</li>

<li><a href="Field-programmable_gate_array" title="Field-programmable gate array">Field-programmable gate array</a> (FPGA)</li>

<li><a href="Field-programmable_object_array" title="Field-programmable object array">Field-programmable object array</a> (FPOA)</li>

<li><a href="Application-specific_integrated_circuit" title="Application-specific integrated circuit">Application-specific integrated circuit</a> (ASIC)</li>

<li><a href="Tensor_Processing_Unit" title="Tensor Processing Unit">Tensor Processing Unit</a> (TPU)</li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;">Theory</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Digital_signal" title="Digital signal">Digital signal</a></li>

<li><a href="Boolean_algebra" title="Boolean algebra">Boolean algebra</a></li>

<li><a href="Logic_synthesis" title="Logic synthesis">Logic synthesis</a></li>

<li><a href="Logic_in_computer_science" title="Logic in computer science">Logic in computer science</a></li>

<li><a href="Computer_architecture" title="Computer architecture">Computer architecture</a></li>

<li><a href="Digital_signal_(signal_processing)" title="Digital signal (signal processing)">Digital signal</a>

<ul><li><a href="Digital_signal_processing" title="Digital signal processing">Digital signal processing</a></li></ul></li>

<li><a href="Circuit_minimization_for_Boolean_functions" class="mw-redirect" title="Circuit minimization for Boolean functions">Circuit minimization</a></li>

<li><a href="Switching_circuit_theory" title="Switching circuit theory">Switching circuit theory</a></li>

<li><a href="Gate_equivalent" title="Gate equivalent">Gate equivalent</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;"><a href="Electronics_design" class="mw-redirect" title="Electronics design">Design</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Logic_synthesis" title="Logic synthesis">Logic synthesis</a></li>

<li><a href="Place_and_route" title="Place and route">Place and route</a>

<ul><li><a href="Placement_(electronic_design_automation)" title="Placement (electronic design automation)">Placement</a></li>

<li><a href="Routing_(electronic_design_automation)" title="Routing (electronic design automation)">Routing</a></li></ul></li>

<li><a href="Transaction-level_modeling" title="Transaction-level modeling">Transaction-level modeling</a></li>

<li><a href="Register-transfer_level" title="Register-transfer level">Register-transfer level</a>

<ul><li><a href="Hardware_description_language" title="Hardware description language">Hardware description language</a></li>

<li><a href="High-level_synthesis" title="High-level synthesis">High-level synthesis</a></li></ul></li>

<li><a href="Formal_equivalence_checking" title="Formal equivalence checking">Formal equivalence checking</a></li>

<li><a href="Synchronous_circuit" title="Synchronous circuit">Synchronous logic</a></li>

<li><a href="Asynchronous_circuit" title="Asynchronous circuit">Asynchronous logic</a></li>

<li><a href="Finite-state_machine" title="Finite-state machine">Finite-state machine</a>

<ul><li><a href="Hierarchical_state_machine" class="mw-redirect" title="Hierarchical state machine">Hierarchical state machine</a></li></ul></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;">Applications</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Computer_hardware" title="Computer hardware">Computer hardware</a>

<ul><li><a href="Hardware_acceleration" title="Hardware acceleration">Hardware acceleration</a></li></ul></li>

<li><a href="Digital_audio" title="Digital audio">Digital audio</a>

<ul><li><a href="Digital_radio" title="Digital radio">radio</a></li></ul></li>

<li><a href="Digital_photography" title="Digital photography">Digital photography</a></li>

<li><a href="Telephony#Digital_telephony" title="Telephony">Digital telephone</a></li>

<li><a href="Digital_video" title="Digital video">Digital video</a>

<ul><li><a href="Digital_cinematography" title="Digital cinematography">cinematography</a></li>

<li><a href="Digital_television" title="Digital television">television</a></li></ul></li>

<li><a href="Electronic_literature" title="Electronic literature">Electronic literature</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;">Design issues</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Metastability_(electronics)" title="Metastability (electronics)">Metastability</a></li>

<li><a href="Runt_pulse" title="Runt pulse">Runt pulse</a></li></ul>

</div></td></tr></tbody></table></div>

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